The invention relates to polishing pads for chemical mechanical planarization (CMP) and electrochemical mechanical planarization (ECMP), and in particular relates to conductive polishing pads for same.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from the surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials are deposited by a number of deposition techniques. Common deposition techniques include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., metallization) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
CMP is a common technique used to planarize substrates such as semiconductor wafers. In conventional CMP, a wafer carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the wafer, urging it against the polishing pad. The pad is optionally moved (e.g., rotated) relative to the wafer by an external driving force. Simultaneously therewith, a chemical-base polishing fluid (e.g., a slurry) is flowed onto the polishing pad and into the gap between the wafer and the polishing pad. The wafer surface is thus polished and made planar by the chemical and mechanical action of the pad surface and polishing fluid.
There is presently a demand in integrated circuit (IC) manufacturing for increasing densities of backend wiring interconnects. Further, there is increasing use of IC fabrication techniques using multiple conductive layers and damascene processes with low dielectric insulators. In manufacturing ICs using these techniques, planarizing the various layers is a critical step in the IC manufacturing process.
Moreover, the mechanical aspect of CMP is reaching the limit of its ability to planarize such IC substrates because the layers cannot handle the mechanical stress of polishing. In particular, delamination and fracture of the underlayer cap and dielectric material occurs during CMP due to frictional stress induced by the physical contact between the polishing substrate and the polish pad.
To mitigate detrimental mechanical effects associated with CMP such as those described above, one approach is to perform ECMP in the manner described in U.S. Pat. No. 5,807,165 while another related approach is to perform electropolishing using a non-contact method in the manner described in International Patent No. WO 00/03426.
By way of background, ECMP is a controlled electrochemical dissolution process. The planarization mechanism is the diffusion-controlled dissolution of metals M (e.g., copper) on the substrate surface using an applied voltage.
In conventional ECMP, the electrochemical reaction takes place in the following order:                1. Charge transfer: M→M++e−;        2. the accumulation of metal ions (M+) on the substrate surface;        3. the acceptor diffuses to the metal surface;        4. the complex is formed between the acceptor and metal ions; and        5. the diffusion of the complex from the surface into the electrolytic polishing solution.        
The acceptor during electrochemical polishing is a complexing agent in the electrochemical polishing solution. In the case of copper, the acceptor can be water and any of the known copper complexing agents. The coordination number is generally 6 and the state of copper ions is +2.
On an uneven substrate surface, prior to electrochemical polishing the charge transfer step (step 1) converts the metal (M) to metal ions (M+) adsorbed on the metal on the surface. This reaction is uniform and does not smooth the surface (i.e., the surface roughness remains the same at this stage). After executing through steps 1-4, the metallic complex is formed on the metal surface. The diffusion of the metallic complex from the substrate surface into the polishing solution differs between the protruding regions and the recessed regions of the substrate surface. At the protruding regions, the complex diffuses faster than at the recessed regions, ultimately leading to a smooth substrate surface.
On the other hand, for small amounts of surface roughness, the dissolution kinetics is faster for the protruded region even in the absence of electricity because the protruding regions have a higher surface reactivity. This accelerates the planarization process when combined with the diffusion of a metallic complex and a polishing fluid with the appropriate complexing agent. Both micro-leveling and/or macro-leveling electropolishing is enhanced by the mechanical planarization effect from CMP.
In the ECMP and non-contact polishing methods such as those described in the aforementioned patents, the wafer or carrier head must be charged positive and the conductive polish pad or polishing receptacle must be charged negative. To this end, an ECMP tool is employed in which both the carrier and the polish pad are independently connected to a current controller.
It would be greatly beneficial to be able to perform both CMP and ECMP on a CMP tool. However, a conventional CMP polisher cannot be used to carry out ECMP because the carrier head is not easily modified to charge the wafer, and polishing platen or polish pad is not easily modified to conduct currents. Thus, ECMP cannot presently be performed using a CMP tool without significant and expensive physical modifications.